1. Field of the Invention
The present invention relates to static timing analysis and in particular to using samples-based static timing infrastructure for simultaneous multi-corner static timing analysis.
2. Related Art
In sub-65 nm technologies, process and environmental (i.e. voltage and temperature) variations have a significant impact on the timing performance of integrated circuits. To ensure that an integrated circuit design meets the timing requirements in the presence of process and environmental variations, designers can perform static timing analysis for a number of timing “corners”, wherein each corner corresponds to one set of process (e.g., slow, fast, nominal, etc.), voltage, and temperature (PVT) conditions. Statistical static timing (e.g. Monte Carlo samples-based static timing) analysis, which has been developed in the last decade, can address the impact of multiple process corners in a computationally efficient manner, but cannot effectively address the impact of voltage or temperature variations.
As a result, current multi-corner static timing analysis (STA) generally runs one corner at a time (either serially using one tool or in parallel using multiple tools). Generally, the number of corners in current technologies can be in excess of ten corners. After running the corners, the timing results obtained for the corners are merged to obtain a set of critical paths or graph nodes across the multiple corners. Because of the number of corners and the merging of the timing results, significant computational resources are required for current static timing analysis.
Therefore, a need arises for a comprehensive timing solution that can efficiently and accurately perform simultaneous STA of multiple timing corners without using separate runs, and which can also quickly generate summary timing reports without the need for explicit merging.